HMS81032TL datasheet(40/77 Pages) HYNIX

40 / 77 page

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Figure 11-2 CKCTLR AND BITR

BTS[2:0]

CPU Source clock

B.I.T. Input

clock@4Mhz(us)

Standby release

time(ms)

000

001

010

011

100

101

110

111

÷ 8

÷16

÷32

÷64

÷128

÷256

÷512

÷1024

128

256

0.512

1.024

2.048

4.096

8.192

16.384

32.768

65.536

BTCL

BTS1

Basic Interval Timer source clock select

000: fXIN ÷ 8

001: fXIN ÷ 16

010: fXIN ÷ 32

011: fXIN ÷ 64

100: fXIN ÷ 128

101: fXIN ÷ 256

110: fXIN ÷ 512

111: fXIN ÷ 1024

Clear bit

0: Normal operation, free-run

1: Clear 8-bit counter (BITR) to “0” and count up again.

INITAIL VALUE: --110111B

ADDRESS: 0C7H

CKCTLR

INITIAL VALUE: Undefined

ADDRESS: 0C7H

BITR

Both register are in same address,

when write, to be a CKCTLR,

when read, to be a BITR.

Caution:

8-BIT FREE-RUN BINARY COUNTER

BTS0

BTS2

BTCL

ENPCK

This bit becomes to “0” automatically after one machine cycle.

Periphral clock

0:stopped

1:provided

WDTON

Watch Dog Timer function control

0:6bit timer

1:Watch Dog Timer

HMS81032TL Datasheet(PDF) 40 Page - Hynix Semiconductor

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