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HMS81032TL Datasheet(PDF) 47 Page - Hynix Semiconductor |
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HMS81032TL Datasheet(HTML) 47 Page - Hynix Semiconductor |
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47 / 77 page ![]() HMS81004E/08E/16E/24E/32E 44 JUNE 2001 Ver 1.00 2) Timer0, Timer1 TIMER0 and TIMER1 have an up-counter. When value of the up-counter reaches the content of Timer Data Register (TDR), the up-counter is cleared to “00h”, and interrupt (IFT0, IFT1) is occured at the next clock. For Timer0, the internal clock (PS) and the external clock (EC) can be selected as counter clock. But Timer1 and Timer2 use only internal clock. As internal clock. Timer0 can be used as internal-timer which period is determined by Timer Data Register (TDR). Chosen as external clock, Timer0 executes as event-counter. The counter ex- ecution of Timer0 and Timer1 is controlled by T0CN, T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0 and TM1. T0CN, T1CN are used to stop and start Timer0 and Timer1 without clearing the counter. T0ST, T1ST is used to clear the counter. For clearing and starting the counter, T0ST or T1ST should be temporarily set to “0” and then set to “1”. T0CN, T1CN, T0ST and T1ST should be set “1”, when Timer counting-up. Controlling of CAP0 enables Timer0 as input capture. By programming of CAP0 to “1”, the period of signal from INT2 can be measured and then, event counter value for INT2 can be read. During counting-up, value of counter can be read- Timer execution is stopped by the reset signal(RE- SET=”L”) Note: In the process of reading 16-bit Timer Data, first read the upper 8-bit data. Then read the lower 8-bit data, and read the upper 8-bit data again. If the earlier read up- per 8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct. If not, caution should be taken in the selection of upper 8-bit data. (Example) 1) Upper 8-bit Read 0A 0A 2) Lower 8-bit Read FF 01 3) Upper 8-bit Read 0B 0B ===================== 0AFF 0B01 Figure 13-5 Operation of Timer0 Timer 0 (IFT0) Interrupt T0 Data TIME Occur interrupt Occur interrupt Occur interrupt Interrupt period 0 1 2 3 4 5 6 MATCH (TDR = T0) 0 Register Value T0 Value |
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