HMS81032TL datasheet(65/77 Pages) HYNIX

65 / 77 page

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

16.3 Low Voltage Detection Mode

(1) Low voltage detection condition

An on board voltage comparator checks that VDD is at the

required level to ensure correct operation of the device. If

VDD is below a certain level, Low voltage detector forces

the device into low voltage detection mode.

(2) Low Voltage Detection Mode

There is no power consumption except stop current, stop

mode release function is disabled. All I/O port is config-

ured as input mode and Data memory is retained until volt-

age through external capacitor is worn out. In this mode,

all port can be selected with Pull-up resistor by Mask op-

tion. If there is no information on the Mask option sheet

,the default pull up option (all port connect to pull-up resis-

tor ) is selected.

(3) Release of Low Voltage Detection Mode

Reset signal result from new battery(normally 3V) wakes

the low voltage detection mode and come into normal reset

state. It depends on user whether to execute RAM clear

routine or not

Figure 16-4 Timing Diagram of Reset

MAIN PROGRAM

Oscillator

(XIN pin)

FFFE FFFF

Stabilization Time

RESET

ADDRESS

DATA

Start

ADL

ADH

BUS

RESET Process Step

ADL and ADH are start addresses of interrupt service routine as vector contents.

Figure 16-5 Low Voltage vs Temperature

1.55

1.60

1.65

1.70

1.75

1.80

1.85

-25

-20

-15

-10

-5

LVD(V)

Temperature (

°C)

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