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HMS81032TL Datasheet(PDF) 57 Page - Hynix Semiconductor |
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HMS81032TL Datasheet(HTML) 57 Page - Hynix Semiconductor |
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57 / 77 page ![]() HMS81004E/08E/16E/24E/32E 54 JUNE 2001 Ver 1.00 Standby release level control register (SRLC) can select the key scan input level “L” or “H” for standby release by each bit pin (R0, R1). Standby release level control register (SRLC) is write-only register and initialized as “00h” in re- set state. Figure 14-9 Block Diagram of Key Scan Block BTCL 7654 3210 INITIAL VALUE: 00H ADDRESS: 0DCH SMRR0 W KR 07 R03 R02 R0 1 R04 R05 R06 R07 R0 0 R0 PORT LOGIC R13 R12 R1 1 R14 R15 R16 R17 R1 0 SMRR0 SRLC0 R1 PORT LOGIC SMRR1 SRLC1 Internal Key Scan Input W W W W W W W KR 06 KR 05 K R 04 KR 03 KR 02 KR 01 KR 00 KR 0* 1: Select 0: N o S elect BTCL 7654 3210 INITIAL VALUE: 00H ADDRESS: 0DDH SMRR1 W KR 17 W W W W W W W KR 16 KR 15 K R 14 KR 13 KR 12 KR 11 KR 10 KR 1* 1: Select 0: N o S elect BTCL 7654 3210 INITIAL VALUE: 00H ADDRESS: 0F6H SRLC0 W KLR 07 W W W W W W W K LR 06 KLR 05 KLR 04 KLR 03 K LR 02 K LR01 K LR 00 KLR 0* 1: H igh 0: Low BTCL 765 43210 INITIAL VALUE: 00H ADDRESS: 0F7H SRLC1 W KLR 17 W W W W W W W K LR 16 K LR 15 KLR 14 K LR 13 K LR 12 KLR 11 KLR10 KLR 1* 1: H igh 0: Low |
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