HMS81032TL datasheet(56/77 Pages) HYNIX

56 / 77 page

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Response Time

The INT1 ~ INT2 edge are latched into IFINT1 ~ IFINT2 at every

machine cycle. The values are not actually polled by the circuitry

until the next machine cycle. If a request is active and conditions

are right for it to be acknowledged, a hardware subroutine call to

the requested service routine will be the next instruction to be ex-

ecuted. The DIV itself takes twelve cycles. Thus, a minimum of

twelve complete machine cycles elapse between activation of an

external interrupt request and the beginning of execution of the

first instruction of the service routine.

Figure 14-8 shows interrupt response timings.

Figure 14-8 Interrupt Response Timing Diagram

14.8 Key Scan Input Processing

Key Scan Interrupt is generated by detecting low or high

Input from each Input pin (R0, R1) is one of the sources

which release standby (SLEEP, STOP) mode. Key Scan

ports are all 16bit which are controlled by Standby Mode

Release Register (SMRR0, SMRR1). Key Input is consid-

ered as Interrupt, therefore, KSCNE bit of IEHN should be

set for correct interrupt executing, SLEEP mode and STOP

mode, the rest of executing is the same as that of external

Interrupt. Each SMRR Register bit is allowed for each port

(for Bit= “0”, no Key Input, for Bit= “1”, Key Input avail-

able). At reset, SMRR becomes “00h”. So, there is no Key

Input source.

Figure 14-7 External Interrupt Block Diagram

IFINT1

INT1 pin

INT1 INTERRUPT

IFINT2

INT2 pin

INT2 INTERRUPT

IEDS

[0CBH]

Edge selection

BTCL

7654

3210

IED 2H

INITIAL VALUE: 0000_0000B

ADDRESS: 0CBH

IEDS

Ext. Int. Edge Selection reg.

01: Falling Edge Selection

10: Rising Edge Selection

IED2*

11: Both Edsg Selection

WWW

IED 2L IE D 1H

IED 1L

01: Falling Edge Selection

10: Rising Edge Selection

IED1*

11: Both Edsg Selection

Interrupt

goes

active

Interrupt

latched

Interrupt

processing

Interrupt

routine

8 fXIN period

max. 12 fXIN period

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