HMS81032TL datasheet(41/77 Pages) HYNIX

41 / 77 page

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

12. WATCH DOG TIMER

Watch Dog Timer (WDT) consists of 6-bit binary counter,

6-bit comparator, and Watch Dog Timer Register

(WDTR).Watch Dog Timer can be used 6-bit general Tim-

er or specific Watch dog timer by setting bit5 (WDTON)

of Clock Control Register (CKCTLR).By assigning

bit6(WDTCL) of WDTR, 6-bit counter can be cleared.

WDT Interrupt (IFWDT) interval is determined by the in-

terrupt IFBIT interval of Basic Interval Timer and the val-

ue of WDT Register.

-Interval of IFWDT = (IFBIT interval) * (WDTR value)

As IFBIT (Basic Interval Timer Interrupt Request) is used

for input clock of WDT, Input clock cycle is possible from

512 us to 65,536 us by BTS. (at fex = 4MHz)

*At Hardware reset time,WDT starts automatically.

Therefore the user must select the CKCTLR and WDTR

before WDT overflow.

-Reset WDTR value = 0Fh,=15

-Interval of WDT = 65,536 * 15 = 983040 us

(about 1second )

Note : W h en W D TR R e gi st e r va lu e i s 6 3 ( 3 F h )

(Caution) : Do not use “0” for WDTR Register value.

Device come into the reset state by WDT

Figure 12-1 Block diagram of Watch Dog Timer

IFWDT

WDT

INTERRUPT

WDTR (6-bit)

WDT (6-bit)

Comparator

WDT

BTCL

765

432

INITIAL VALUE: -0001111b

ADDRESS: 0C8H

WDTR

WDTCL

[0C8H]

WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0

Watch Dog Timer Operation

0:Free-run

1:Automatically cleared, after one machine cycle

IFBIT

WDTON

To Reset circuit

Clear 6

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