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HMS81032TL Datasheet(PDF) 59 Page - Hynix Semiconductor |
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HMS81032TL Datasheet(HTML) 59 Page - Hynix Semiconductor |
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59 / 77 page ![]() HMS81004E/08E/16E/24E/32E 56 JUNE 2001 Ver 1.00 15.3 STANDBY MODE RELEASE Release of STANDBY mode is executed by RESET input and Interrupt signal. Register value is defined when Reset. When there is a release signal of STOP mode (Interrupt, RESET input), the instruction execution starts after stabi- lization oscillation time is set by value of BTS2 ~ BTS0 and set ENPCK to “1”. Figure 15-1 Block Diagram of Standby Circuit OSC Circuit Clock Pulse Generator CPU Clock Release Signal from Interrupt RESETB STOP S R Q S R Q Control Signal Overflow Detection Prescaler Clear MUX Basic Interval Timer Clear Release Signal SLEEP STOP RESETB O O KSCN(Key Input) O O INT1,INT2 O O B.I.T. O Table 15-1 Release Signal of Standby Mode |
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