HMS81032TL datasheet(51/77 Pages) HYNIX

51 / 77 page

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

14.1 Interrupt priority and sources

Each interrupt vector is independent and has its own pri-

ority. Software interrupt (BRK) is also available. Interrupt

source classification is shown in Table 14-1.

14.2 Interrupt control register

I flag of PSW is a interrupt mask enable flag. When I flag

= “0”, all interrupts become disable. When I flag = “1”, in-

terrupts can be selectively enabled and disabled by con-

tents of corresponding Interrupt Enable Register. When

interrupt is occured, interrupt request flag is set, and Inter-

rupt request is detected at the edge of interrupt signal. The

accepted interrupt request flag is automatically cleared

during interrupt cycle process. The interrupt request flag

maintains “1” until the interrupt is accepted or is cleared in

program. In reset state, interrupt request flag register

(IRQH, IRQL) is cleared to “0”. It is possible to read the

state of interrupt register and to mainpulate the contents of

rupt)

Reset/Interrupt

Symbol

Priority

Hardware Reset

RESET

Key Scan

KSCNR

External Interrupt1

INT1R

External Interrupt2

INT2R

Timer0

T0R

Timer1

T1R

Timer2

T2R

Watch Dog Timer

WDTR

Basic Interval Timer

BITR

BRK Instruction

BRK

Table 14-1 Interrupt Source

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