UM0434 datasheet(233/390 Pages) STMICROELECTRONICS

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Instruction pipeline and execution timing

UM0434

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8.8

Operand placement on performance

The placement (location and alignment) of operands in memory affects relative performance

of memory accesses, and in some cases, affects it significantly.

Table 164 indicates the

effects for the e200z3 core.

Table 164, ‘optimal’ means that one EA calculation occurs during the operation; ‘good’

means that multiple EA calculations occur during the memory operation, which may cause

additional bus activities with multiple bus transfers; ‘poor’ means that the access generates

an alignment interrupt.

efsmul

efsnabs

efsneg

efsnmadd

Destination also used as source

efsnmsub

Destination also used as source

efssub

efststeq

efststgt

efststlt

Table 163.

Scalar SPE Floating-Point instruction timing (continued)

Instruction

Latency

Throughput

Comments

Table 164.

Performance effects of storage operand placement

Operand

Boundary crossing*

Size

Byte alignment

None

Cache Line

Protection

boundary

4 byte

optimal

good

2 byte

optimal

good

1 byte

optimal

lmw, stmw

good

poor

good

poor

good

poor

String

N/A

Optimal: One EA calculation occurs.

Good: Multiple EA calculations occur, which may cause additional bus activities with multiple bus

transfers.

Poor: Alignment Interrupt occurs.

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