UM0434 datasheet(237/390 Pages) STMICROELECTRONICS

237 / 390 page

External core complex interfaces

UM0434

238/391

Table 165 below, shows the core signal function and type, signal definition, and reset value.

Signals are presented in functional groups.

Table 165.

Interface signal definitions

Signal name

I/O Reset

Definition

Clock and signals related to reset

m_clk

Global system clock

m_por

Power-on reset

p_reset_b

Processor reset input

p_resetout_b

Processor reset output

p_rstbase[0:19]

Reset exception handler base address, value to be loaded into

TLB entry 0 on reset.

p_rst_endmode

Reset endian mode select, value to be loaded into TLB entry 0

on reset.

p_rst_vlemode

Reset VLE mode select, value to be loaded into TLB entry 0 on

reset.

Memory interface signals

p_i_hmaster[3:0],

p_d_hmaster[3:0]

O—

Master ID

p_i_haddr[31:0],

p_d_haddr[31:0]

—

Address bus

p_i_hwrite,

p_d_hwrite

Write signal (always driven low for

p_i_hwrite)

p_i_hprot[5:0],

p_d_hprot[5:0]

—

Protection codes

p_i_htrans[1:0],

p_d_htrans[1:0]

—

Transfer type

p_i_hburst[2:0] ,

p_d_hburst[2:0]

O—

Burst type

p_i_hsize[1:0],

p_d_hsize[1:0]

—

Transfer size

p_i_hunalign,

p_d_hunalign

—

Indicates that the current data access is misaligned

p_i_hbstrb[7:0] ,

p_d_hbstrb[7:0]

Byte strobes

p_i_hrdata[63:0],

p_d_hrdata[63:0]

Read data bus

p_d_hwdata[63:0]

—

Write data bus

p_i_hready,

p_d_hready

Transfer ready

p_i_hresp[2:0],

p_d_hresp[2:0]

Transfer response

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