UM0434 datasheet(240/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

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9.3

Signal descriptions

Table 166 describes the processor clock, m_clk.

Table 167 describes signals that are related to reset. The core supports several reset input

signals for the CPU and JTAG/OnCE control logic:

m_por, p_reset_b, and j_trst_b. The reset

domains are partitioned such that the CPU

p_reset_b signal does not affect JTAG/OnCE

logic and

j_trst_b does not affect processor logic. It is possible and desirable to access

OnCE registers while the processor is running or in reset. It is also possible and desirable to

assert

j_trst_b and clear the JTAG/OnCE logic without affecting the processor state.

The synchronization logic between the processor and debug module requires an assertion

of either

j_trst_b or m_por during initial processor power-on reset to ensure proper

operation. If the pin associated with

j_trst_b is designed with a pull-up resistor and left

floating, assertion of

m_por is required during the initial power-on processor reset. Similarly,

for those systems that do not have a power-on reset circuit and choose to tie

m_por low, it is

required to assert

j_trst_b during processor power-up reset. When a power-up reset is

achieved, the two resets can be asserted independently.

A reset output signal,

p_resetout_b, is also provided.

j_shift_ir

Shift_IR state of JTAG controller

j_capture_dr

Parallel test data register load state of JTAG controller

j_shift_dr

TAP controller in shift DR state

j_update_gp_reg

Updates JTAG controller test data register

j_rti

JTAG controller run-test-idle state

j_key_in

Input for providing data to be shifted out during shift_IR state

when

jd_en_once is negated

j_en_once_regsel

External enable OnCE register select

j_nexus_regsel

External Nexus register select

j_lsrl_regsel

External LSRL register select

j_gp_regsel[0:11]

General-purpose external JTAG register select

j_id_sequence[0:1]

JTAG ID register (2 msbs of sequence field)

j_id_version[0:3]

JTAG ID register version field

j_serial_data

Serial data from external JTAG registers

Table 165.

Interface signal definitions (continued)

Signal name

I/O Reset

Definition

Table 166.

Processor clock signal description

Signal I/O

Signal description

m_clk

Processor clock. The synchronous clock source for the core. Because the core is

designed for static operation,

m_clk can be gated off to lower power dissipation (for

example, during low-power stopped states).

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