UM0434 datasheet(244/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

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p_[d,i]_hburst[2:0]] O

Burst type. The core uses only SINGLE and WRAP4 burst types.

000 SINGLE—No burst, single beat only

001 INCR—Incrementing burst of unspecified length. Not used by the core.

p_[d,i]_hprot[5:0]

Protection control. The core drives the

p_[d,i]_hprot[5:0] signals to indicate the type of

access for the current bus cycle.

p_[d,i]_hprot[0] indicates instruction/data,

p_[d,i]_hprot[1] indicates user/supervisor. p_[d,i]_hprot[5] indicates whether the access is

exclusive (that is, for an lwarx or stwcx.).

p_[d,i]_hprot[4:2] (allocate, cacheable,

bufferable) indicate particular cache attributes for the access. The following table shows

the definitions of the

p_[d,i]_hprot[5:0] signals.

p_hprot5

p_hprot4 p_hprot3 p_hprot2

p_hprot1

p_hprot0

Transfer Type

—

Instruction access

—

Data access

—

User mode access

—

Supervisor mode

access

—

Cache-inhibited

—

Guarded, not

cache-inhibited

—0

—

Reserved

—0

—

Reserved

—1

—

Reserved

—1

—

Reserved

—

Cacheable,

writethrough

—

Cacheable,

writeback

—

Not exclusive

—

Exclusive access

The core maps Book E storage attributes to the AHB hprot signals as described in the

following. For buffered stores,

p_[d,i]_hprot[1] is driven with the user/supervisor mode

attribute associated with the store at the time it was buffered. For cache line

pushes/copybacks,

p_[d,i]_hprot[1] indicates supervisor access. In both of these cases,

p_[d,i]_hprot0 indicates a data access.

TLB[I] TLB[G] TLB[W]||!L1CSR0[CWM]

p_hprot[4:2]

Transfer Type

111

Cacheable, writeback

110

Cacheable, writethrough

—

001

Guarded, not cache-inhibited

—

000

Cache-inhibited

—

001

Buffered store, page marked

guarded

—

110

Buffered store and page

marked writethrough or

L1CSR0[CWM]=0, and non-

guarded

—

111

Buffered store and page

marked copyback and

L1CSR0[CWM]=1, and non-

guarded

—

111

Dirty line push

Table 169.

Descriptions of transfer attribute signals (continued)

Signal

I/O

Signal description

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