UM0434 datasheet(246/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

247/391

Table 172 shows the final layout in memory for data transferred from a 64-bit GPR containing the bytes ‘A

B C D E F G H’ to memory. The core breaks misaligned accesses that cross a double-word boundary into

a pair of accesses. Double-word transfers are always double-word–aligned.

Byte @011

0 1 1

0 0

—

Byte @100

1 0 0

0 0

—

Byte @101

1 0 1

0 0

—

————

—

Byte @110

1 1 0

0 0

—

————

—

Byte @111

1 1 1

0 0

—

————

——

Half @000

0 0 0

0 1

—

Half @001

0 0 1

1 0(1)

—

———

Half @010

0 1 0

0 1

—

Half @011

0 1 1

1 1 1

—

———

Half @100

1 0 0

0 1

—

Half @101

1 0 1

—

————

—

Half @110

1 1 0

0 1

—

————

—

Half @111

(Two bus transfers)

1 1 1

0 0 0

0 1(2)

0 0

—

Word @000

0 0 0

1 0

—

Word @001

0 0 1

1 1 1

—

XXXX

—

Word @010

0 1 0

1 1 1

—

XXX

—

Word @011

0 1 1

1 1 1

——

—

Word @100

1 0 0

1 0

—

Word @101

(Two bus transfers)

1 0 1

0 0 0

1 0

0 0

—

Word @110

(Two bus transfers)

1 1 0

0 0 0

1 0 2

0 1

—

Word @111

(Two bus transfers)

1 1 1

0 0 0

1 0 2

1 0

—

Double word

0 0 0

1 1

XXXX

XXX

These misaligned transfers drive size according to the size of the power of two aligned containers in which the byte strobes

are asserted.

These misaligned cases drive request size according to the size specified by the load or store instruction.

Table 171.

Byte strobe assertion for transfers (continued)

Program size and

byte offset

A(2:0)

HSIZE

[1:0]

Data bus byte strobes

HUNALIGN

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