UM0434 datasheet(245/390 Pages) STMICROELECTRONICS

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External core complex interfaces

UM0434

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Table 170 describes signals for byte lane specification. Read transactions transfer from 1–8 bytes of data

on the

p_[d,i]_hrdata[63:0] bus. The lanes involved in the transfer are determined by the starting byte

number specified by the lower address bits with the transfer size and byte strobes. Byte lane addressing

is shown big-endian (left to right) regardless of the core’s endian mode. The byte in memory

corresponding to address 0 is connected to B0 (

p_h{r,w}data[7:0]) and the byte corresponding to address

7 is connected to B7 (

p_h{r,w}data[63:56]). The CPU internally permutes read data as required for the

endian mode of the current access. Assertion of

p_[d,i]_hunalign indicates misaligned transfers and that

byte strobes do not correspond exactly to size and low-order address bits.

Table 171 lists all data transfer permutations. Note that misaligned data requests that cross a 64-bit

boundary are broken into two bus transactions, and the address value and size encoding for the first

transfer are not modified. The table is arranged in a big-endian fashion, but the active lanes are the same

regardless of the endian-mode of the access. The core performs the proper byte routing internally based

on endianness.

Table 170.

Descriptions of signals for byte lane specification

Signal

I/O

Signal description

p_[d,i]_hunalign

Unaligned access. Indicates whether the current access is misaligned.

State

Meaning

Asserted—Asserted for misaligned data accesses and for misaligned instruction

accesses from VLE pages. Normal Book E instruction pages are always aligned.

When

p_[d,i]_hunalign is asserted, the p_[d,i]_hbstrb[7:0] byte strobe signals

indicate the selected bytes involved in the current portion of the misaligned

access, which may not include all bytes defined by the size and low-order

address signals. Aligned transfers also assert the byte strobes, but in a manner

corresponding to size and low-order address bits.

Negated—No misaligned data access is occurring.

Timing The timing of this signal is approximately the same as address timing.

p_[d,i]_hbstrb[7:0] O

Byte strobes. Indicate the bytes selected for the current transfer. For a misaligned access,

the current transfer may not include all bytes defined by the size and low-order address

signals. For aligned transfers, the byte strobe signals correspond to the bytes that size and

low-order address signals define. The relationships of byte addresses to the byte strobe

signals are as follows.

Memory byte address

Wired to p_h{r,w}data bits

Corresponding byte strobe

signal

000

7:0

p_[d,i]_hbstrb[0]

001

15:8

p_[d,i]_hbstrb[1]

010