UM0434 datasheet(242/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

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Table 168 describes signals for the address and data buses. These outputs provide the address for a bus

transfer. According to the AHB definition,

p_haddr31 is the msb and p_haddr0 is the lsb.

j_trst_b

JTAG/OnCE reset (IEEE 1149.1 JTAG specification TRST).

State

Meaning

Asynchronous reset with a short assertion time requirement. It is ORed with the

m_por function, and the resulting signal clears the OnCE TAP controller and

associated registers and the OnCE state machine.

Table 167.

Descriptions of signals related to reset (continued)

Signal

I/O

Signal description

Table 168.

Descriptions of signals for the address and data buses

Signal

I/O

Signal description

p_[d,i]_haddr[31:0]

Address bus. Provides the address for a bus transfer. According to the AHB definition,

p_[d,i]_haddr[31] is the msb and p_[d,i]_haddr[0] is the lsb.

p_[d,i]_hrdata[63:0]

Read data bus. Provides data to the core on read transfers. The read data bus can

transfer 8, 16, 24, 32, or 64 bits per transfer. According to the AHB definition,

p_[d,i]_hrdata63 is the msb and p_[d,i]_hrdata0 is the lsb.

Memory Byte AddressWired to

p_[d,i]_hrdata Bits

0007:0

00115:8

01023:16

01131:24

10039:32

10147:40

11055:48

11163:56

p_d_hwdata[63:0]

Write data bus. Transfers data from the core on write transfers. The write data bus can

transfer 8, 16, 24, 32, or 64 bits of data per bus transfer. According to the AHB definition,

p_d_hwdata[63] is the msb and p_d_hwdata[0] is the lsb.

Memory Byte AddressWired to

p_d_hwdata Bits

0007:0

00115:8

01023:16

01131:24

10039:32

10147:40

11055:48

11163:56

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