UM0434 datasheet(239/390 Pages) STMICROELECTRONICS

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External core complex interfaces

UM0434

240/391

p_wakeup

Indicates to external clock control module to enable clocks and

exit from low-power mode

p_halt

CPU halt request

p_halted

CPU halted

p_stop

CPU stop request

p_stopped

CPU stopped

CPU debug event signals

p_ude

Unconditional debug event

p_devt1

Debug event 1 input

p_devt2

Debug event 2 input

Debug/Emulation support signals (Nexus 1/OnCE)

jd_en_once

Enable full OnCE operation

jd_debug_b

Processor entered debug session

jd_de_b

Debug request

jd_de_en

Active-high output enable for DE_b open-drain IO cell

jd_mclk_on

System clock controller actively toggling

m_clk

jd_watchpt[0:7]

Address watchpoint occurred

Development support signals (Nexus 3)

nex_mcko

Nexus3 clock output

nex_rdy_b

Nexus3 ready output

nex_evto_b

Nexus3 event-out output

nex_evti_b

Nexus3 event-in input

nex_mdo[n:0]

Nexus3 message data output

nex_mseo_b[1:0]

Nexus3 message start/end output

JTAG-Related signals

j_trst_b

JTAG test reset from pad

j_tclk

JTAG test clock from pad

j_tms

JTAG test mode select from pad

j_tdi

JTAG test data input from pad

j_tdo

JTAG test data out to master controller or pad

j_tdo_en

Enables TDO output buffer

j_tst_log_rst

Test-logic-reset state of JTAG controller

j_capture_ir

Capture_IR state of JTAG controller

j_update_ir

Update_IR state of JTAG controller

Table 165.

Interface signal definitions (continued)

Signal name

I/O Reset

Definition

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