UM0434 datasheet(243/390 Pages) STMICROELECTRONICS

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External core complex interfaces

UM0434

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Table 169 describes transfer attribute signals, which provide additional information about the bus transfer

cycle. Attributes are driven with the address at the start of a transfer.

Table 169.

Descriptions of transfer attribute signals

Signal

I/O

Signal description

p_[d,i]_htrans[1:0]

Transfer type. The processor drives

p_[d,i]_htrans[1:0] to indicate the current transfer type

as follows:

00 DLE—No data transfer is required. Slaves must terminate IDLE transfers with a zero

wait-state OKAY response and ignore the (non-existent) transfer.

01 BUSY—(The core does not use the BUSY encoding and does not present this type of

transfer to a bus slave.) Master is busy; burst transfer continues.

10 NONSEQ—Indicates the first transfer of a burst, or a single transfer. Address and

control signals are unrelated to the previous transfer.

11 SEQ—Indicates the continuation of a burst. Address and control signals are related to

the previous transfer. Control signals are the same. Address was incremented by the size

of the data transferred (optionally wrapped).

If the

p_[d,i]_htrans[1:0] encoding is not IDLE or BUSY, a transfer is being requested.

p_[d,i]_hwrite

Write. Defines the data transfer direction for the current bus cycle.

State

Meaning

Asserted—The current bus cycle is a write.

Negated—The current bus cycle is a read.

p_[d,i]_hsize[1:0]

Transfer size. For misaligned transfers, size may exceed the requested size to ensure that

all asserted byte strobes are within the container defined by

p_[d,i]_hsize[1:0]. Table 171

and

Table 172 show p_[d,i]_hsize encodings for aligned and misaligned transfers.

00 Byte

01 Half word (2 bytes)

10 Word (4 bytes)

11 Double word (8 bytes)

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