UM0434 datasheet(250/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

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Table 173 describes the transfer control signals.

Table 174 describes the master ID configuration signals. These inputs drive the p_[d,i]_hmaster[3:0]

outputs when a bus cycle is active.

Table 175 describes interrupt control signals. Interrupt request inputs (p_extint_b, p_critint_b, and

p_mcp_b) to the core are level-sensitive. The interrupt controller must keep the interrupt request and any

L. E. Word @1111

1 1 1 1

1 0

—

———

——

———

——

+ 0 0 0 0

(next dword)

1 0

——

———

——

———

——

—

B.E. Double word

- 0 0 0

1 1

—

———

——

—

L.E. Double word

- 0 0 0

1 1

—

These misaligned transfers drive size according to the size of the power of two aligned containers in which the byte strobes

are asserted.

Table 172.

Big-and Little-Endian storage (64-Bit GPR contains ‘A B C D E F G H’) (continued)

Program size and

byte offset

A(3:0)

HSIZE

(1:0)

Even double Word— 0

0dd double Word—1

B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7

Table 173.

Descriptions of signals for transfer control signals

Signal

I/O

Signal description

p_[d,i]_hready

Transfer ready. Indicates whether a requested transfer operation has completed. An external

device asserts

p_[d,i]_hready to terminate the transfer. p_hresp[2:0] indicate the transfer

status.

State

Meaning

Asserted—A requested transfer operation has completed. An external device

asserts

p_[d,i]_hready to terminate the transfer.

Negated—A requested transfer operation has not completed.

p_hresp[2:0]

Transfer response. Indicate status of a terminating transfer.

000 OKAY—Transfer terminated normally.

001 ERROR—Transfer terminated abnormally. See note for assertion.

010 Reserved (RETRY not supported in AHB-Lite protocol)

011 Reserved (SPLIT not supported in AHB-Lite protocol)

100 XFAIL—Exclusive store failed (stwcx. did not complete successfully). See note for

assertion. (Signaled to the CPU using the

p_xfail_b internal signal. See Table 190.)

101–111 Reserved

Timing

Assertion—ERROR and XFAIL are required to be 2-cycle responses that must be

signaled one cycle before assertion of

p_[d,i]_hready and must remain unchanged

during the cycle

p_[d,i]_hready is asserted. The XFAIL response is signaled to the

CPU using the

p_xfail_b internal signal.

Table 174.

Descriptions of master ID configuration signals

Signal

I/O

Signal description

p_masterid[3:0]

CPU master. Configures the master ID for the CPU. Driven on

p_[d,i]_hmaster[3:0] for a

CPU-initiated bus cycle.

nex_masterid[3:0]

Nexus3 master. Configure the master ID for the Nexus3 unit. Driven on

p_[d,i]_hmaster[3:0] for a Nexus3-initiated bus cycle.

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