UM0434 datasheet(253/390 Pages) STMICROELECTRONICS

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UM0434

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Table 177 describes the processor reservation signals associated with lwarx and stwcx..

Table 178 describes miscellaneous processor signals.

p_tbint

Timer interrupt status. Indicates whether an internal timer facility unit is requesting an interrupt

(TSR[WIS]=1 and TCR[WIE]=1, or TSR[DIS]=1 and TCR[DIE]=1, or

TSR[FIS]=1 and TCR[FIE]=1). May be used to exit low power operation or for other system

purposes.

State

Meaning

Asserted—An internal timer facility unit is generating an interrupt request.

Negated—An internal timer facility unit is not generating an interrupt request.

Table 176.

Descriptions of timer facility signals (continued)

Signal

I/O

Signal description

Table 177.

Descriptions of processor reservation signals

Signal

I/O

Signal description

p_rsrv

CPU reservation status. Indicates whether a reservation was established by the execution of an

lwarx.

State

Meaning

Asserted—A reservation was established by successful execution of an lwarx.

Remains asserted until the reservation is cleared.

Negated—No reservation is in effect.

Timing Assertion—Remains asserted until the reservation is cleared.

p_rsrv_clr

CPU reservation clear. Used to clear a reservation. External logic may use this signal to

implement reservation management policies outside the scope of the CPU.

p_xfail_b indicates

success/failure of an stwcx. as part of bus transfer termination using the XFAIL

p_hresp[2:0]

encoding.

State

Meaning

Asserted—Signals that a reservation should be cleared. Asserted independently of

any bus transfer.

Timing Assertion—Asserted independently of any bus transfer.

Table 178.

Descriptions of miscellaneous processor signals

Signal

I/O

Signal description

p_cpuid[0:7]

CPU ID. Reflected in the PIR. See

Chapter 4.4.2: Processor ID register (PIR) on page 45.”

Timing Intended to remain in a static condition and are not internally synchronized.

p_pid0[0:7]

PID0 outputs. Reflected to PID0[56–63]. See

Chapter 4.16.5: Process ID register (PID0) on

page 96.”

p_pid0_updt

PID0 update. Indicates that PID0 is being updated by an mtspr.

State

Meaning

Asserted—PID0 is being updated by an mtspr.

Negated—PID0 is not being updated by an mtspr.

Timing Assertion—asserts during the clock cycle the

p_pid0[0:7] outputs are changing

p_sysvers[0:31]

System version. Core version number reflected in the SVR. See

Chapter 4.4.4: System

version register (SVR) on page 46.”

Timing Intended to remain in a static condition and not internally synchronized.

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