UM0434 datasheet(252/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

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Table 176 describes the timer facility signals, which are associated with the time base, watchdog, fixed-

interval, and decrementer facilities.

p_voffset[0:15

]

Interrupt vector offset. Vector offset and context selector used when processing begins for an

incoming interrupt request. Ignored if multiple hardware contexts are not implemented.

State

Meaning

Correspond to IVOR

n[16–31]. p_voffset[0:11] are used in forming the exception

handler address;

p_voffset[12:15] are used to select a new operating context when

multiple hardware contexts are implemented.

Timing

Sampled with the

p_extint_b and p_critint_b interrupt request inputs; must be

driven to a valid value when either signal is asserted unless

p_avec_b is also

asserted. If

p_avec_b is asserted, these inputs are not used.

Assertion—Level-sensitive; must remain asserted to guarantee correct recognition.

Must be asserted concurrently with

p_extint_b and p_critint_b when used.

p_iack

Interrupt vector acknowledge. Interrupt vector acknowledge indicator to allow external interrupt

controllers to be informed when a critical input or external input interrupt is being processed.

State

Meaning

Asserted—An interrupt vector is being acknowledged.

Negated—An interrupt vector is not being acknowledged.

Timing

Assertion—Asserted after the cycle in which

p_avec_b and p_voffset[0:15] are

sampled in preparation for exception processing. See

Figure 62 and <Cross

Refs>Figure 63 for timing diagrams.

p_mcp_b

Machine check. Machine check interrupt request to the core. Masked by HID0[EMCP].

State

Meaning

Asserted—A machine check interrupt is being requested.

Negated—A machine check interrupt is not being requested.

Timing

Because this signal is not internally synchronized by the core, it must meet setup

and hold time constraints to

m_clk when the core clock is running. p_mcp_b is not

sampled while the core is in the halted or stopped power management states.

Assertion—

p_mcp_b is sampled on two consecutive m_clk periods to detect a

transition from the negated to the asserted state. It is internally qualified with this

transition, but must remain asserted to be guaranteed to be recognized

Table 175.

Descriptions of interrupt signals (continued)

Signal

I/O

Signal description

Table 176.

Descriptions of timer facility signals

Signal

I/O

Signal description

p_tbdisable

Timer disable. Used to disable the internal time base and decrementer counters. Used to freeze

the state of the time base and decrementer during low power or debug operation.

State

Meaning

Asserted—Time base and decrementer updates are frozen.

Negated—Time base and decrementer updates are unaffected.

Timing

Not internally synchronized by the core; must meet setup and hold time constraints

relative to

m_clk when the core clock is running, as well as to p_tbclk when selected

as an alternate time base clock source.

p_tbclk

Timer external clock. Used as an alternate clock source for the time base and decrementer

counters. Selection of this clock is made using HID0[SEL_TBCLK] (see

Chapter 4.13.1:

Hardware implementation dependent register 0 (HID0) on page 84”).

Timing

Must be synchronous to the

m_clk input and cannot exceed 50% of the m_clk

frequency. Must be driven such that it changes state on the falling edge of

m_clk.

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