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UM0434

External core complex interfaces

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External core complex interfaces

This chapter describes the external interfaces of the e200z3 core complex. Signal

descriptions as well as data transfer protocols are documented in the following subsections.

Chapter 9.4: Internal signals on page 265,” describes a number of internal signals that are

not directly accessible to users, but they are mentioned in various chapters in this manual

and aid in understanding the behavior of the core.

9.1

Overview

The external interfaces encompass the following:

●

Control and data signals supporting instruction and data transfers

●

Support for interrupts, including vectored interrupt logic

●

Reset support

●

Power management interface signals

●

Debug event signals

●

Time base control and status information

●

Processor state information

●

Nexus 1/3/OnCE/JTAG interface signals

●

A test interface

The memory interface that the BIU supports is based on the AMBA AHB-Lite subset of the

AMBA 2.0 AHB, with V6 AMBA extensions. (Ref. documents ARM IHI 0011A, ARM DVI

0044A, and ARM PR022-GENC-001011 0.4). Sideband signals, described in this chapter,

support additional control functions. A 64-bit data bus is implemented. The pipelined

memory interface supports read and write transfers of 8, 16, 24, 32, and 64 bits, misaligned

transfers, burst transfers of four double words, and true big- and little-endian operation.

Note:

The AMBA AHB bit and byte ordering reflect a natural little-endian ordering that AMBA

documentation uses. The BIU automatically performs byte lane conversions to support big-

endian transfers. Memories and peripheral devices/interfaces should be wired according to

byte lane addresses defined in Table 170.

Single-beat and misaligned transfers are supported for cache-inhibited read and write

cycles, and write-buffer writes. Burst transfers (double-word–aligned) of 4 double words are

supported for cache line-fill and copyback operations.

Misaligned accesses are supported with one or more transfers to the core interface. If an

access is misaligned but lies within an aligned 64-bit double word, the core performs a

single transfer. The memory interface delivers (reads) or accepts (writes) the data that

corresponds to the size- and byte-enable signals aligned according to the 3 low-order

address bits. If an access is misaligned and crosses a 64-bit boundary, the BIU performs a

pair of transfers beginning at the effective address, requesting the original data size (either

half word or word) for the first transfer, along with appropriate byte enables. For the second

transfer, the address is incremented to the next 64-bit boundary, and the size and byte

enable signals are driven to correspond to the number of remaining bytes to be transferred.

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