UM0434 datasheet(317/390 Pages) STMICROELECTRONICS

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Debug support

UM0434

318/391

11.5.7

Methods for entering debug mode

The OSR indicates that the CPU has entered the debug mode through the debug status bit.

The following sections describe how debug mode is entered assuming the OnCE circuitry

has been enabled.

OnCE operation is enabled by the assertion of the

jd_en_once input (see Table 195).

DBSR

*(1)

Reads of DBSR while the CPU is

running may not give data that is self-

consistent due to synchronization

across clock domains.

IAC1

*(1)

IAC2

*(1)

IAC3

*(1)

IAC4

*(1)

JTAG ID

—

Read only

OCR

OSR

—

Read only, accessed by scanning out

IR while

jd_en_once is set

PC FIFO

—

Read only, updates frozen while

OCMD holds PCFIFO register

encoding

Note: PCFIFO cannot be updated

while the OnCE state machine is in

Test_Logic_Reset state

Cache debug

access control

(CDACNTL)

CPU must be in debug mode with

clocks running

Cache debug

access data

(CDADATA)

CPU must be in debug mode with

clocks running

Nexus3-Access

External GPRs

LSRL Select

System test logic implementation

determines LSRL functionality

Writes to these registers while the CPU is running may have unpredictable results due to the pipelined nature of the

operation and the fact that updates are not synchronized to a particular clock, instruction, or bus cycle boundary; therefore,

it is strongly recommended to ensure the processor is first placed into debug mode before updates to these registers are

performed.

Table 205.

OnCE register access requirements (continued)

Access requirements

Notes

jd_en_once

to be Set

DBCR0

[EDM] = 1

m_clk

active

for

Write

Access

CPU to

Halted

for Read

Access

CPU to

Halted

for

Write

Access

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