UM0434 datasheet(313/390 Pages) STMICROELECTRONICS

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Debug support

UM0434

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2EX

Exit. The Exit command is executed only if the Go command is issued and the operation is a

read/write to CPUSCR or a read/write to no register selected. Otherwise, the EX bit is ignored.

The processor leaves debug mode after the TAP controller Update-DR state is entered. Note that if

the DR bit in the OnCE control register is set or remains set, or if a bit in the DBSR is set, or if a bit in

the DBSR is set and DBCR0[EDM] = 1 (external debug mode is enabled), then the processor may

return to the debug mode without execution of an instruction, even though the EX bit was set.

0 Remain in debug mode

1 Leave debug mode. The processor leaves debug mode and resumes normal operation until

another debug request is generated.

3–9

operation.

Table 205 indicates the OnCE register addresses. Attempted writes to read-only registers

are ignored.

000 0000–000 0001 Reserved

000 0010 JTAG ID read–only

000 0011–000 1111 Reserved

001 0000 CPU scan register CPUSCR

001 0001 No register selected bypass

001 0010 OnCE control register OCR

001 0011–001 1111 Reserved

010 0000 Instruction address compare 1 IAC1

010 0001 Instruction address compare 2 IAC2

010 0010 Instruction address compare 3 IAC3

010 0011 Instruction address compare 4 IAC4

010 0100 Data address compare 1 DAC1

010 0101 Data address compare 2 DAC2

010 0110 Reserved DVC1 future use

010 0111 Reserved DVC2 future use

010 1000–010 1011 Reserved

010 1100 Debug counter register DBCNT

010 1101 Debug PCFIFO (PCFIFO) read–only

010 1110–010 1111 Reserved

011 0000 Debug status register DBSR

011 0001 Debug control register 0 DBCR0

011 0010 Debug control register 1 DBCR1

011 0011 Debug control register 2 DBCR2

011 0100 Debug control register 3 DBCR3

011 0101–101 1111 Reserved (do not access)

111 0000–111 1001 General purpose register selects [0–9]

111 1010–111 1011 Reserved

111 1100 Nexus3–Access–See

Chapter 12: Nexus3 module on page 329.”

111 1101 Reserved

111 1110 Enable_OnCE(1)

Causes assertion of the

j_en_once_regsel output. Refer to Chapter : OnCE control register (OCR) on page 315.”

Table 202.

OCMD field descriptions (continued)

Bits Name

Description

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