UM0434 datasheet(312/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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Table 202.

OCMD field descriptions

Bits Name

Description

0R/W

Read/Write. Specifies the direction of data transfer.

0 Write the data associated with the command into the register specified by RS

1 Read the data contained in the register specified by RS

Note: R/W is generally ignored for read-only or write-only registers, although the PC FIFO pointer is

only guaranteed to be updated when R/W = 1. In addition, it is ignored for all bypass operations.

When performing writes, most registers are sampled in the Capture-DR state into a 32-bit shift

j_tdo during the first 32 clocks of Shift-DR.

1GO

Go. If the GO bit is set, the chip executes the instruction which resides in the IR register in the

CPUSCR. To execute the instruction, the processor leaves debug mode, executes the instruction,

and, if the EX bit is cleared, returns to debug mode immediately after executing the instruction. The

processor goes on to normal operation if the EX bit is set, and no other debug request source is set.

The GO command is executed only if the operation is a read/write to CPUSCR or a read/write to no

controller Update-DR state is entered.

On a Go+NoExit operation, returning to debug mode is treated as a debug event; thus, exceptions

such as machine checks and interrupts may take priority and prevent execution of the intended

instruction. Debug firmware should mask these exceptions as appropriate. OSR[ERR] indicates

such an occurrence.

0 Inactive (no action taken)

1 Execute instruction in IR

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