UM0434 datasheet(308/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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CPU address and attributes

The CPU address and attribute information are used by an external Nexus class 2–4 debug

unit with information for real-time address trace information.

CPU data

The CPU data bus is used to supply an external Nexus class 2–4 debug unit with

information for real-time data trace capability.

11.5.4

OnCE interface signals

The following sections describe additional OnCE interface signals to other external blocks

such as a Nexus controller and external blocks that may need information pertaining to

debug operation.

Table 198 describes the OnCE interface signals.

Table 198.

OnCE interface signals

Signal name

I/O

Description

OnCE enable

(

jd_en_once)

The OnCE enable signal,

jd_en_once, is used to enable the OnCE controller to allow

certain instructions and operations to be executed. Assertion of this signal enables the

full OnCE command set, as well as operation of control signals and OnCE control

Enable_OnCE commands are executed by the OnCE unit, and all other commands

default to the Bypass command. The OSR is not visible when OnCE operation is

disabled. Also OCR functions are also disabled, as is the operation of the

jd_de_b

input. Secure systems may choose to leave

jd_en_once negated until a security check

has been performed. Other systems should tie this signal asserted to enable full

OnCE operation. The

j_en_once_regsel output signal is provided to assist external

logic performing security checks. Refer to

Chapter : OnCE control register (OCR) on

page 315,” for a description of the j_en_once_regsel output.

The

jd_en_once input must change state only during the test-logic-reset, Run-

Test/Idle, or Update-DR TAP states. A new value takes effect after one additional

j_tclk

cycle of synchronization. In addition,

jd_enable_once must not change state during a

debug session, or undefined activity may occur.

OnCE debug

request

(

jd_de_b)/event

(jd_de_en)

I/O

The system-level bidirectional open drain debug event pin,

DE_b, (not part of the

interface described in

Chapter 9: External core complex interfaces on page 235”)

provides a fast means of entering the debug mode of operation from an external

command controller (when input) as well as a fast means of acknowledging entry into

debug mode of operation to an external command controller (when output). The

assertion of this pin by a command controller causes the CPU core to finish the

current instruction being executed, save the instruction pipeline information, enter

debug mode, and wait for commands to be entered. If

DE_b was used to enter debug

mode,

DE_b must be negated after the OnCE controller responds with an

acknowledge and before sending the first OnCE command. The assertion of this pin

by the CPU core acknowledges that it has entered the debug mode and is waiting for

commands to be entered. To support operation of this system pin, the OnCE logic

supplies the

jd_de_en output and samples the jd_de_b input when OnCE is enabled

(

jd_en_once set). Assertion of jd_de_b causes the OnCE logic to place the CPU into

debug mode. Once debug mode has been entered, the

jd_de_en output is asserted

for three

j_tclk periods to signal an acknowledge; jd_de_en can be used to enable the

open-drain pulldown of the system level

DE_b pin.

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