UM0434 datasheet(307/390 Pages) STMICROELECTRONICS

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Debug support

UM0434

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instruction and returns to the debug state (again indicated by the OSR). The debug session

remains in force until the final Go+Exit command is executed, at which time the CPU returns

to its previous state (unless a new debug request is pending). A scan into the CPUSCR is

required before executing each Go+Exit or Go+NoExit command.

11.5.2

JTAG/OnCE signals

The JTAG/OnCE interface is used to transfer OnCE instructions and data to the OnCE

control block. Depending on the resource being accessed, the CPU may need to be placed

in debug mode. For resources outside the CPU block and contained in the OnCE block, the

processor is not disturbed and may continue execution. If a processor resource is required,

an internal debug request (

dbg_dbgrq) may be asserted to the CPU by the OnCE controller,

and causes the CPU to finish the instruction being executed, save the instruction pipeline

information, enter debug mode, and wait for further commands. Asserting

dbg_dbgrq

causes the chip to exit the low-power mode enabled by setting MSR[WE].

Table 196 details the primary JTAG/OnCE interface signals.

A full description of JTAG signals is provided in

Chapter 9.3.2: JTAG ID signals.”

11.5.3

OnCE internal interface signals

The following sections describe the OnCE interface signals to other internal blocks

associated with the OnCE controller.

Table 197 shows the OnCE internal interface signals.

Table 196.

JTAG/OnCE primary interface signals

Signal name

I/O

Description

j_trst_b

JTAG test reset

j_tclk

JTAG test clock

j_tms

JTAG test mode select

j_tdi

JTAG test data input

j_tdo

Test data out to master controller or pad

j_tdo_en

Enables TDO output buffer. Set when the TAP controller is

in the Shift-DR or Shift-IR state.

Table 197.

OnCE internal interface signals

Signal name

I/O

Description

CPU Debug

Request

(

dbg_dbgrq)

The db

g_dbgrq signal is set by the OnCE control logic to request the

CPU to enter the debug state. It may be set for a number of different

conditions, and causes the CPU to finish the current instruction being

executed, save the instruction pipeline information, enter debug mode,

and wait for further commands.

CPU Debug

Acknowledge

(

cpu_dbgack)

The

cpu_dbgack signal is set by the CPU upon entering the debug

state. This signal is used as part of the handshake mechanism between

the OnCE control logic and the rest of the CPU. The CPU core may

enter debug mode through either a software or hardware event.

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