UM0434 datasheet(303/390 Pages) STMICROELECTRONICS

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Debug support

UM0434

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11.5

External debug support

External debug support is supplied through the core’s OnCE controller serial interface,

which allows access to internal CPU registers and other system state while in external

debug mode (DBCR0[EDM] is set). All debug resources, including DBCR0–DBCR3, DBSR,

IAC1–IAC4, DAC1, DAC2 and DBCNT are accessible through the serial on-chip emulation

(OnCE) interface in external debug mode. Setting the DBCR0[EDM] bit through the OnCE

interface enables external debug mode and disables software updates to the debug

registers. When DBCR0[EDM] is set, debug events enabled to set respective DBSR status

Return Debug

Event

RET

A return debug event occurs if return debug events are enabled (DBCR0[RET] = 1)

and an attempt is made to execute an rfi instruction. This event can occur and be

recorded in DBSR regardless of the setting of MSR[DE]. When a return debug

event occurs, the DBSR[RET] bit is set so the debug exceptions are recorded.

If MSR[DE] = 0 and DBCR0[EDM] = 0 when rfi executes (that is, before the MSR is

updated by the rfi), DBSR[IDE] is also set to record the imprecise debug event.

If MSR[DE] = 1 when rfi executes, a debug interrupt occurs provided no higher

priority exception is enabled to cause an interrupt. DSRR0 holds the address of the

rfi instruction.

Critical Return

Debug Event

CRET

A critical return debug event occurs if critical return debug events are enabled

(DBCR0[CRET] = 1) and an attempt is made to execute an rfci instruction. This

event can occur and be recorded in DBSR regardless of the setting of MSR[DE].

When a critical return debug event occurs, the DBSR[CRET] bit is set to record the

debug exception.

If MSR[DE] = 0 and DBCR0[EDM] = 0 at the time of the execution of the rfci (that is

before the MSR is updated by the rfci), DBSR[IDE] is also set to record the

imprecise debug event.

If MSR[DE] = 1 at the time of the execution of the rfci, a debug interrupt occurs

provided no higher priority exception is enabled to cause an interrupt. Debug

save/restore register 0 is set to the address of the rfci instruction. Note that this

debug event should not normally be enabled unless the debug APU is also enabled

to avoid corruption of CSRR0 or CSRR1.

Debug Counter

Debug Event

DCNT1,

DCNT2

A debug counter debug event occurs if debug counter debug events are enabled

(DBCR0[DCNT1] = 1 or DBCR0[DCNT2] = 1), a debug counter is enabled, and a

counter decrements to zero. This event can occur and be recorded in DBSR

regardless of the setting of MSR[DE]. When a debug counter debug event occurs,

DBSR[DCNT1] or DBSR[DCNT2] is set to record the debug exception.

External Debug

Event

DEVT1,

DEVT2

An external debug event occurs if external debug events are enabled

(DBCR0[DEVT1] = 1 or DBCR0[DEVT2] = 1), and the respective

p_devt1 or

p_devt2 input signal transitions to the set state. This event can occur and be

recorded in DBSR regardless of the setting of MSR[DE]. When an external debug

event occurs, DBSR[DEVT1] or DBSR[DEVT2] is set to record the debug

exception.

Unconditional

Debug Event

UDE

An unconditional debug event occurs when the unconditional debug event (

p_ude)

input transitions to the set state, and either DBCR0[IDM] = 1 or DBCR0[EDM] = 1.

The unconditional debug event is the only debug event that does not have a

corresponding enable bit for the event in DBCR0. This event can occur and be

recorded in DBSR regardless of the setting of MSR[DE]. When an unconditional

debug event occurs, DBSR[UDE] is set, so debug exceptions are recorded.

Table 195.

Debug event descriptions (continued)

Event name

Type

Description

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