UM0434 datasheet(304/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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bits also cause the CPU to enter debug mode, as opposed to generating debug interrupts.

In debug mode, the CPU is halted at a recoverable boundary, and an external debug control

module may control CPU operation through the OnCE logic. No debug interrupts can occur

while DBCR0[EDM] remains set.

Note:

On the initial setting of DBCR0[EDM], other bits in DBCR0 are unchanged. After

DBCR0[EDM] is set, all debug register resources may be subsequently controlled through

the OnCE interface. DBSR should be cleared as part of the process of enabling external

debug activity. The CPU should be placed into debug mode through the OCR[DR] control bit

before setting EDM. This allows the debugger to cleanly write to the DBCRn registers and

the DBSR to clear out any residual state/control information that could cause unintended

operation.

Note:

It is intended for the CPU to remain in external debug mode (DBCR0[EDM] = 1) in order to

single-step or perform other debug mode entry/reentry through the OCR[DR], by performing

OnCE Go+NoExit commands, or by assertion of jd_de_b.

Note:

DBCR0[EDM] operation is blocked if the OnCE operation is disabled (jd_en_once negated)

regardless of whether it is set or cleared. This means that if DBCR0[EDM] was previously

set and then jd_en_once is negated (this should not occur), entry into debug mode is

blocked, all events are blocked, and watchpoints are blocked.

Due to clock domain design, the CPU clock (

m_clk) must be active for writes to be

performed to debug registers other than the OnCE command register (OCMD), the OnCE

control register (OCR), or DBCR0[EDM]. Register read data is synchronized back to the

j_tclk clock domain. The OnCE control register provides the capability of signaling the

system level clock controller that the CPU clock should be activated if not already active.

Updates to DBCR

n, DBSR, and DBCNT through the OnCE interface should be performed

with the CPU in debug mode to guarantee proper operation. Due to the various points in the

CPU pipeline where control is sampled and event handshaking is performed, it is possible

that modifications to these registers while the CPU is running may result in early or late

entry into debug mode and incorrect status information posted in DBSR.

11.5.1

OnCE introduction

The on-chip emulation circuitry (OnCE/Nexus class 1 interface) provides a means of

interacting with the core and integrated system so that a user may examine registers,

memory, or on-chip peripherals. OnCE operation is controlled through an industry-standard

IEEE 1149.1 TAP controller. By using JTAG instructions, the external hardware debugger

can freeze or halt the CPU, read and write internal state, and resume normal execution. The

core does not contain IEEE 1149.1 standard boundary cells on its interface, as it is a

building block for further integration. It does not support the JTAG-related boundary scan

instruction functionality, although JTAG public instructions may be decoded and signaled to

external logic.

The OnCE logic provides for Nexus class 1 static debug capability (using the same set of

resources available to software while the core is in internal debug mode), and is present in

all e200z3-based designs. The OnCE module also provides support for directly integrating a

Nexus class 2 or class 3 real-time debug unit with the core for development of real-time

systems where traditional static debug is insufficient. The partitioning between a OnCE

module and a connected Nexus module to provide real-time debugging allows for capability

and cost tradeoffs to be made.

The core is designed to be a fully integratable module. The OnCE TAP controller and

associated enabling logic are designed to allow concatenation with an existing JTAG

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