UM0434 datasheet(306/390 Pages) STMICROELECTRONICS

306 / 390 page

UM0434

Debug support

307/391

Figure 68.

OnCE controller as an FSM

Access to core processor registers and the contents of memory locations is performed by

enabling external debug mode (setting DBCR0[EDM]), placing the processor into debug

mode, and scanning instructions and data into and out of the core CPU scan chain

(CPUSCR); execution of scanned instructions by the core is used as the method for

accessing required data. Memory locations may be read by scanning a load instruction into

the core that references the desired memory location, executing the load instruction, and

then scanning out the result of the load. Other resources are accessed in a similar manner.

The initial entry by the CPU into the debug state (or mode) from normal, stopped, halted, or

checkstop states (all indicated by the OnCE status register (OSR) described in

Chapter :

OnCE status register (OSR) on page 311”) by assertion of one or more debug requests

begins a debug session. The

jd_debug_b output signal indicates that a debug session is in

progress, and the OSR indicates that the CPU is in the debug state. Instructions may be

single-stepped by scanning new values into the CPUSCR and performing a OnCE

Go+NoExit command (see

Chapter : OnCE command register (OCMD) on page 312”). The

CPU then temporarily exits the debug state (but not the debug session) to execute the

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select DR-Scan

Run-Test/Idle

Test-Logic-Reset

Select IR-Scan

UM0434 Datasheet(PDF) 306 Page - STMicroelectronics