UM0434 datasheet(309/390 Pages) STMICROELECTRONICS

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Debug support

UM0434

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11.5.5

OnCE controller and serial interface

The OnCE controller contains the OnCE command register, the OnCE decoder, and the

status/control register.

Figure 69 is a block diagram of the OnCE controller. In operation, the

OnCE command register acts as the instruction register (IR) for the TAP controller, and all

other OnCE resources are treated as data registers (DR) by the TAP controller. The

command register is loaded by serially shifting in commands during the TAP controller Shift-

IR state, and is loaded during the Update-IR state. The command register selects a

resource to be accessed as a data register (DR) during the TAP controller Capture-DR,

Shift-DR, and Update-DR states.

OnCE debug

output

(jd_debug_b)

The OnCE debug output

jd_debug_b is used to indicate to on-chip resources that a

debug session is in progress. Peripherals and other units may use this signal to modify

normal operation for the duration of a debug session, which may involve the CPU

executing a sequence of instructions solely for the purpose of visibility/system control

that are not part of the normal instruction stream the CPU would have executed had it

not been placed in debug mode. This signal is set the first time the CPU enters the

debug state, and remains set until the CPU is released by a write to the core OnCE

command register (OCMD) with the GO and EX bits set, and a register specified as

either no register selected or the CPUSCR. This signal remains set even though the

CPU may enter and exit the debug state for each instruction executed under control of

the OnCE controller. See

Chapter : OnCE command register (OCMD) on page 312,”

for more information on the function of the GO and EX bits. This signal is not normally

used by the CPU.

CPU clock on input

(jd_mclk_on)

The CPU clock on input (

jd_mclk_on) is used to indicate that the CPU’s m_clk input is

active. This input signal is expected to be driven by system logic external to the core,

is synchronized to the

j_tclk (scan clock) clock domain and presented as a status flag

on the

j_tdo output during the Shift-IR state. External firmware may use this signal to

ensure proper scan sequences occur to access debug resources in the

m_clk clock

domain.

Watchpoint events

(

jd_watchpt[0:7])

The

jd_watchpt[0:7] signals may be set by the OnCE control logic to signal that a

watchpoint condition has occurred. Watchpoints do not cause the CPU to be affected.

They are provided to allow external visibility only. Watchpoint events are conditioned

by the settings in DBCR0, DBCR1, and DBCR2.

Table 198.

OnCE interface signals (continued)

Signal name

I/O

Description

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