UM0434 datasheet(311/390 Pages) STMICROELECTRONICS

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Debug support

UM0434

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OnCE command register (OCMD)

The OnCE command register (OCMD) is a 10-bit shift register that receives its serial data

from the TDI pin and serves as the instruction register (IR). It holds the 10-bit commands to

be used as input for the OnCE decoder. OCMD is shown in

Table 202. It is updated when

the TAP controller enters the Update-IR state. It contains fields for controlling access to a

resource, as well as controlling single-step operation and exit from OnCE mode.

Although OCMD is updated during the Update-IR TAP controller state, the corresponding

resource is accessed in the DR scan sequence of the TAP controller, and as such, the

Update-DR state must be transitioned through for an access to occur. In addition, the

Update-DR state must also be transitioned through in order for the single-step and/or exit

functionality to be performed, even though the command appears to have no data resource

requirement associated with it.

Table 202 describes OCMD fields.

RESET

Reset mode. Reflects the inverted logic level on the CPU

p_reset_b input after

capture by

j_tclk.

4HALT

Halt mode. Reflects the logic level on the CPU

p_halted output after capture by

j_tclk.

5STOP

Stop mode. Reflects the logic level on the CPU

p_stopped output after capture by

j_tclk.

6DEBUG

Debug mode. Set once the CPU is in debug mode. It is negated once the CPU

exits debug mode (even during a debug session).

—

Reserved, set to 0

—

Reserved, set to 0 for 1149.1 compliance

—

Reserved, set to 1 for 1149.1 compliance

Table 201.

OCMD fields

Field

R/W

Reset

0b10_0000_0010 on assertion of

j_trst_b or m_por or while in test-logic-reset state

Table 200.

OSR field descriptions (continued)

Bits

Name

Description

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