UM0434 datasheet(310/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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Figure 69.

OnCE controller and serial interface

OnCE status register (OSR)

Status information regarding the state of the CPU is latched into the OSR when the OnCE

controller state machine enters the Capture-IR state. When OnCE operation is enabled, this

information is provided on the

j_tdo output in serial fashion when the Shift-IR state is

entered following a Capture-IR. Information is shifted out least-significant bit first.

Table 199.

OnCE status register (OSR)

Table 200 describes OnCE status register bits.

789

Field

MCLK

ERR

CHKSTOP RESET

HALT

STOP

DEBUG

Table 200.

OSR field descriptions

Bits

Name

Description

0MCLK

m_clk status bit. Reflects the logic level on the jd_mclk_on input signal after

capture by

j_tclk.

0 Inactive state

1 Active state

1ERR

Error. Used to indicate that an error condition occurred during attempted execution

of the last single-stepped instruction (Go+NoExit with CPUSCR or no register

selected in OCMD), and that the instruction may not have executed properly. This

can occur if an interrupt (all classes including external, critical, machine check,

storage, alignment, program, TLB, and so on) occurs while attempting to perform

the instruction single-step. In this case, CPUSCR contains information related to

the first instruction of the interrupt handler, and no portion of the handler will have

executed.

CHKSTOP

Checkstop mode. Reflects the logic level on the CPU

p_chkstop output after

capture by

j_tclk.

OnCE Command Register

TDI

TCLK

Status and Control

Registers

TDO

Mode Select

OnCE Decoder

CPU

Update

Read

Write

Control/

Status

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