UM0434 datasheet(302/390 Pages) STMICROELECTRONICS

302 / 390 page

UM0434

Debug support

303/391

Instruction

Complete Debug

Event

IAC

An instruction-complete debug event occurs if instruction-complete debug events

are enabled (DBCR0[ICMP] = 1), execution of any instruction is completed, and

MSR[DE] = 1 or DBCR0[EDM] = 1. If execution of an instruction is suppressed due

to the instruction causing some other exception that is enabled to generate an

interrupt, then the attempted execution of that instruction does not cause an

instruction complete debug event. The sc instruction does not fall into the category

of an instruction whose execution is suppressed, since the instruction actually

executes and then generates a system call interrupt. In this case, the instruction

complete debug exception is also set. When an instruction complete debug event is

recognized, DBSR[ICMP] is set to record the debug exception, and the address of

the next instruction to be executed is recorded in DSRR0.

Instruction complete debug events are not recognized if MSR[DE] = 0 and

DBCR0[EDM] = 0 at the time of execution of the instruction; thus, DBSR[IDE] is not

generally set by an ICMP debug event.

One circumstance may cause DBSR[ICMP] and DBSR[IDE] to be set. This occurs

when an embedded FPU round exception occurs. Because the instruction is by

definition completed (SRR0 points to the following instruction), this interrupt takes

higher priority than the debug interrupt so as not to be lost, and DBSR[IDE] = 1 to

indicate imprecise recognition of a debug interrupt. In this case, the debug interrupt

is taken with SRR0 pointing to the instruction following the instruction that

generated the SPEFPU round exception, and DSRR0 points to the round exception

handler. In addition to occurring when DBCR0[IDM] = 1, this circumstance can also

occur when DBCR0[EDM] = 1.

Instruction complete debug events are not generated by the execution of an

instruction that sets MSR[DE] while DBCR0[ICMP] = 1, nor by the execution of an

instruction that sets DBCR0[ICMP] while MSR[DE] = 1 or DBCR0[EDM] = 1.

Interrupt Taken

Debug Event

IRPT

An interrupt-taken debug event occurs if interrupt-taken debug events are enabled

(DBCR0[IRPT] = 1) and a non-critical interrupt occurs. Only non-critical class

interrupts cause an interrupt-taken debug event. This event can occur and be

recorded in DBSR regardless of the setting of MSR[DE]. When an interrupt-taken

debug event occurs, DBSR[IRPT] is set to record the debug exception. DSRR0

holds the address of the non-critical interrupt handler.

Critical Interrupt

Taken Debug

Event

CIRPT

A critical interrupt taken debug event occurs if critical interrupt taken debug events

are enabled (DBCR0[CIRPT] = 1) and a critical interrupt (other than a debug

interrupt when the debug APU is disabled) occurs. Only critical class interrupts

cause a critical-interrupt-taken debug event. This event can occur and be recorded

in DBSR regardless of the setting of MSR[DE]. When a critical-interrupt-taken

debug event occurs, DBSR[CIRPT] bit is set, ensuring that debug exceptions are

recorded. DSRR0 holds the address of the critical interrupt handler.

To avoid corruption of CSRR0 or CSRR1, this debug event should not normally be

enabled unless the debug APU is also enabled.

Table 195.

Debug event descriptions (continued)

Event name

Type

Description

UM0434 Datasheet(PDF) 302 Page - STMicroelectronics

UM0434 Datasheet(HTML) 302 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL