UM0434 datasheet(298/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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11.4

Software debug events and exceptions

Software debug events and exceptions are available if internal debug mode is enabled

(DBCR0[IDM] = 1) and not overridden by external debug mode (DBCR0[EDM] = 0). When

enabled, debug events cause debug exceptions to be recorded in the debug status register.

Specific event types are enabled by DBCR0–DBCR3. The unconditional debug event (UDE)

is an exception to this rule; it is always enabled. Once a DBSR bit other than MRR and

CNT1TRG is set, if debug interrupts are enabled by MSR[DE], a debug interrupt is

generated. The debug interrupt handler is responsible for ensuring that multiple repeated

debug interrupts do not occur by clearing the DBSR as appropriate.

Certain debug events are not allowed to occur when MSR[DE] = 0 and DBCR0[EDM] = 0.

Under these conditions, no debug exception occurs and thus no DBSR bit is set. Other

debug events may cause debug exceptions and set DBSR bits regardless of the state of

MSR[DE]. A debug interrupt is delayed until MSR[DE] is set.

When a DBSR bit is set while MSR[DE] = 0 and DBCR0[EDM] = 0, an imprecise debug

event flag (DBSR[IDE]) is also set to indicate that an exception bit in the DBSR was set

while debug interrupts were disabled. The debug interrupt handler software can use this bit

to determine whether DSRR0 holds the address associated with the instruction causing the

debug exception or the address of the instruction that enabled a delayed debug interrupt by

setting MSR[DE]. An mtmsr or mtdbcr0, which causes both MSR[DE] and DBCR0[IDM] to

be set, enabling precise debug mode, may cause an imprecise (delayed) debug exception to

be generated due to an earlier recorded event in the DBSR.

The following types of debug events are defined by Book E:

●

Instruction address compare debug events

●

Data address compare debug events

●

Trap debug events

●

Branch taken debug events

●

Instruction complete debug events

●

Interrupt taken debug events

●

Return debug events

●

Unconditional debug events

These events are described in further detail in the

EREF.

IAC2

Instruction address compare 2

313

R/W

Yes

IAC3

Instruction address compare 3

314

R/W

Yes

IAC4

Instruction address compare 4

315

R/W

Yes

DAC1

Data address compare 1

316

R/W

Yes

DAC2

Data address compare 2

317

R/W

Yes

The DBSR can be read using mfspr rD,DBSR. It cannot be directly written to. Instead, DBSR bits

corresponding to 1 bits in GPR(rS) can be cleared using mtspr DBSR,rS.

Table 194.

Debug registers (continued)

Mnemonic

Name

SPR

number

Access

Privileged

Core

specific

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