UM0434 datasheet(296/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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access all system resources and perform the necessary functions appropriate for system

debugging.

PowerPC book E compatibility

The core implements a subset of the PowerPC Book E internal debug features. The

following restrictions on functionality are present:

●

Instruction address compares do not support compare on physical (real) addresses.

●

Data address compares do not support compare on physical (real) addresses.

●

Data value compares are not supported.

11.2.2

Additional debug facilities

In addition to the debug functionality defined in Book E, the core provides the capability to

link instruction and data breakpoints. The core also provides a configurable debug event

counter to allow debug exception generation and a sequential breakpoint control

mechanism.

The core also defines two new debug events (critical interrupt taken and critical return) for

debugging around critical interrupts.

In addition, the core implements the debug auxiliary processing unit (APU) which, when

enabled, allows debug interrupts to use a dedicated set of save/restore registers (DSRR0

and DSRR1) to save state information when a debug interrupt occurs and restore this state

information at the end of a debug interrupt handler with the rfdi instruction.

11.2.3

Hardware debug facilities

The core contains facilities that allow for external test and debugging. A modified

IEEE 1149.1 control interface is used to communicate with core resources. This interface is

implemented through a standard 1149.1 TAP (test access port) controller.

By using public instructions, the external debugger can freeze or halt the core, read and

write internal state and debug facilities, single-step instructions, and resume normal

execution.

Hardware debug is enabled by setting the external debug mode enable bit (DBCR0[EDM]).

Setting DBCR0[EDM] overrides the internal debug mode enable bit DBCR0[IDM]. If the

hardware debug facility is enabled, software is blocked from modifying the debug facilities. In

addition, because resources are owned by the hardware debugger, inconsistent values may

be present if software attempts to read debug-related resources.

When hardware debug is enabled (DBCR0[EDM] = 1), the registers and resources

described in

Chapter 11.3: Debug registers,” are reserved for use by the external debugger.

The events described in

Chapter 11.3: Debug registers,” are also used for external

debugging, but exceptions are not generated to running software. Debug events enabled in

the respective DBCR0–DBCR3 registers are recorded in the DBSR regardless of MSR[DE],

and no debug interrupts are generated. Instead, the CPU enters debug mode when an

enabled event causes a DBSR bit to become set. DBCR0[EDM] may only be written through

the OnCE port.

A program trace program counter FIFO (PC FIFO) is also provided to support program

change-of-flow capture.

To perform write accesses from the external hardware debugger, most debug resources

(registers) require the CPU clock (

m_clk) to be running.

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