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Power management

UM0434

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10.1.2

Power management control bits

Software uses the register fields listed in

Table 193 to generate a request to enter a power-

saving state and to choose the state to be entered.

10.1.3

Software considerations for power management

Setting MSR[WE] generates a request to enter a power-saving state (doze, nap, or sleep).

This state must be previously determined by setting the appropriate HID0 bit. Setting

MSR[WE] does not directly affect execution, but is reflected on

p_doze, p_nap, and p_sleep,

depending on the setting of the HID0 DOZE, NAP, and SLEEP bits. Note that the core is not

affected by assertion of these signals directly. External system hardware may interpret the

state of these signals and activate the

p_halt and/or p_stop inputs to cause the core to enter

a quiescent state, in which clocks may be disabled for low-power operation.

To ensure a clean transition into and out of a power-saving mode, the following program

sequence is recommended:

sync

mtmsr (WE)

isync

loop:br loop

An interrupt is typically used to exit a power-saving state. The

p_wakeup output is used to

indicate to the system logic that an interrupt (or a debug request) has become pending.

System logic uses this output to re-enable the clocks and exit a low-power state. The

interrupt handler is responsible for determining how to exit the low-power loop if one is used.

p_tbclk

Timer external clock. Used as an alternate clock source for the time base and

decrementer counters. Selection of this clock is made using HID0[SEL_TBCLK]

(see

Chapter 4.13.1: Hardware implementation dependent register 0 (HID0) on

page 84”).

p_tbint

Timer interrupt status. Indicates whether an internal timer facility unit is requesting

an interrupt (TSR[WIS] = 1 and TCR[WIE] = 1, or TSR[DIS] = 1 and

TCR[DIE] = 1, or TSR[FIS] = 1 and TCR[FIE] = 1). May be used to exit low-power

operation or for other system purposes.

Table 193.

Power management control bits

Bit

Description

MSR[WE]

Used to qualify assertion of the

p_doze, p_nap, and p_sleep outputs to the integrated

logic. When MSR[WE] is negated, these signals are negated. If MSR[WE] is set,

these pins reflect the state of their respective HID0 control bits.

HID0[DOZE]

The interpretation of the DOZE mode bit is done by the external integrated logic.

Doze mode on the core is intended to be the halted state with the clocks running.

HID0[NAP]

The interpretation of the NAP mode bit is done by the external integrated logic. Nap

mode on the core may be used for a power-down state with the time base enabled.

HID0[SLEEP]

The interpretation of the SLEEP mode bit is done by the external integrated logic.

Sleep mode on the core may be used for a power-down state with the time base

disabled.

Table 192.

Descriptions of timer facility and power management signals (continued)

Signal

I/O

Signal description

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