UM0434 datasheet(290/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

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In this example, an external input interrupt is requested in cycle 1. The

p_voffset[0:15]

inputs are driven with the vector offset for ‘A’, and

p_avec_b is negated, indicating vectoring

is desired. For this example, the bus is idle at the time of assertion. The CPU may sample a

requested interrupt as early as the cycle in which it is initially requested, and it does so in

this example. The interrupt request,the vector offset, and the autovector input are sampled

at the end of cycle 1. In cycle 3, the interrupt is acknowledged by the assertion of the

p_iack

output, indicating that the values present on interrupt inputs at the beginning of cycle 2 have

been internally latched and committed for servicing. Note that the interrupt vector lines have

changed to a value of ‘B’ during cycle 2, and the

p_critint_b input has been asserted by the

interrupt controller. The vector number and autovector signals must be consistent with the

higher priority critical input request, and thus must change when the state of the interrupt

request inputs change. The

p_iack output assertion in cycle 3 indicates that the values

present at the rise of cycle 2 (vector ‘A’) have been committed to. During cycle 3, the CPU

begins instruction fetching of the handler for vector ‘A’. The new request for a subsequent

critical interrupt ‘B’ was not received in time to be acted on first. It is acknowledged after the

fetch for the external input interrupt handler is completed and has entered decode.

Note that the time between assertion of an interrupt request input and the acknowledgment

of an interrupt may be multiple cycles, and the interrupt inputs may change during that

interval. The CPU asserts the

p_iack output to indicate the cycle at which an interrupt is

committed to. In the following example, because the CPU was unable to acknowledge the

external input interrupt during cycle 2 due to internal or external execution conditions, the

critical input request was sampled. This case is shown in

Figure 63.

Interrupt acknowledge operation case 2

vec A

vec B

B handler

B +8

idle

1 outst.

2 outst.

int B handlr

B hand + 8

int B hand addr int B hand + 8

m_clk

p_critint_b

p_extint_b

p_voffset[0:15]

sample point

p_iack

p_avec_b

p_treq_b

p_addr

attributes

p_r/w

p_tbusy_b

p_data_in

p_ta_b

mmu access

cache access

cache miss

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