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Power management

UM0434

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Power management

This chapter describes the power management facilities as they are defined by Book E and

implemented in devices that contain the core. The scope of this chapter is limited to core

complex features. Additional power management capabilities associated with a device that

integrates this core (referred to as an integrated device) are documented separately.

10.1

Overview

Power management minimizes overall system power consumption. The core provides the

ability to initiate power management from external sources as well as through software

techniques.

Table 191 describes core power states.

Table 191.

Power states

State

Description

Active

(Default)

All internal units on the core operate at full processor clock speed. The core provides

dynamic power management in which idle internal units may stop clocking automatically.

Halted

Instruction execution and bus activity are suspended, and most internal clocks are gated

off. The core asserts

p_halted to indicate it is in the halted state. Before entering halted

state, all outstanding bus transactions complete, and the cache’s store and push buffers

are flushed. The

m_clk input should remain running to allow further transitions into the

power-down state if requested and to keep the time base operational if it is using

m_clk as

the clock source.

Power

down

(stopped)

All core functional units except the time base unit and clock control state machine logic

are stopped.

m_clk may be kept running to keep the time base active and to allow quick

recovery to full-on state. Clocks are not running to functional units except to the time

base. The core reaches power-down state after transitioning through halted state with

p_stop asserted; at this point p_stopped output is asserted.

Additional power may be saved by disabling the time base by asserting

p_tbdisable or by

integrated logic stopping

m_clk after the core is in power-down state and has asserted

p_stopped.

To exit power-down state, integrated logic must first restart

m_clk.

Because the time base is off during power-down state, if

m_clk is the clock source and is

stopped, or if time base clocking is disabled by the assertion of

p_tbdisable, system

software must usually have to access an external time base source after returning to the

full-on state to reinitialize the time base unit. A time-base related interrupt source (such as

the decrementer) cannot be used to exit low-power states.

The core also provides the ability to clock the time base from an independent (but

externally synchronized) clock source, which allows the time base to be maintained

during the power-down state, and allows a time-base related interrupt to be generated to

indicate an exit condition from the power-down state.

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