UM0434 datasheet(292/390 Pages) STMICROELECTRONICS

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UM0434

Power management

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Figure 64 is a power management state diagram.

Figure 64.

Power management state diagram

10.1.1

Power management signals

Table 191 summarizes power management signals.

More detailed information is provided in

Chapter 9.5.5: Power management on page 289.”

Halted

Power-Down

p_stop & p_halt

p_stop

p_halt & ~p_stop

p_halt | p_stop

p_stop

Active

p_halt & ~p_stop

(

p_stopped asserted)

(

p_halted asserted)

Table 192.

Descriptions of timer facility and power management signals

Signal

I/O

Signal description

p_halt

Processor halt request. The active-high

p_halt input requests that the core enter

the halted state.

p_halted

Processor halted. The active-high

p_halted output indicates that the core entered

the halted state.

p_stop

Processor stop request. The active-high

p_stop input requests that the core enter

the stopped state.

p_stopped

Processor stopped. The active-high

p_stopped output indicates that the core

entered stopped state.

p_doze

p_nap

p_sleep

Low-power mode. These signals are asserted by the core to reflect the settings of

the HID0[DOZE], HID0[NAP], and HID0[SLEEP] control bits when MSR[WE] is

set. The core can be placed in a low-power state by forcing

m_clk to a quiescent

state, and brought out of low-power state by re-enabling

m_clk. The time base

facilities may be separately enabled or disabled using combinations of the timer

facility control signals.

p_wakeup

Wakeup. Used by external logic to remove the core and system logic from a low-

power state. It can also indicate to the system clock controller that

m_clk should be

re-enabled for debug purposes.

p_wakeup (or other system state) should be monitored to determine when to

release the core (and system if applicable) from a low-power state.

p_tbdisable

Timer disable. Used to disable the internal time base and decrementer counters.

This signal can be used to freeze the state of the time base and decrementer

during low power or debug operation.

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