UM0434 datasheet(295/390 Pages) STMICROELECTRONICS

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Debug support

UM0434

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Debug support

11.1

Introduction

This chapter describes the debug features of the e200z3 core, including the software and

hardware debug facilities, events, and registers. It also details the external debug support

features available and introduces the reader to the on-chip emulation circuitry (OnCE) and

its key attributes, that is, the interface signals, debug inputs, and outputs. This chapter also

covers watchpoint support, MMU and cache operations during debug, cache array access,

and the basic steps for enabling, using, and exiting external debug mode.

11.2

Overview

Internal debug support in the core allows for software and hardware debugging by providing

debug functions such as instruction and data breakpoints and program trace modes. For

software-based debugging, debug facilities consisting of a set of software-accessible debug

registers and interrupt mechanisms are provided. These facilities are also available to a

hardware-based debugger that communicates using a modified IEEE 1149.1 test access

port (TAP) controller and pin interface. When hardware debugging is enabled, the debug

facilities are protected from software modification.

Software debug facilities are defined as part of Book E. The core supports a subset of these

defined facilities. In addition to the Book E–defined facilities, the core provides additional

flexibility and functionality in the form of debug event counters, linked instruction and data

breakpoints, and sequential debug event detection. These features are also available to a

hardware-based debugger.

The core also supports an external Nexus real-time debug module. Real-time system-level

debugging is supported by an external Nexus class 2, 3, or 4 module. Definitions and

features of this module are part of the system/platform specification and are not further

defined in this chapter. Additional information can be found in

Chapter 12: Nexus3 module

on page 329.”

11.2.1

Software debug facilities

The debug facilities enable hardware and software debug functions, such as instruction and

data breakpoints and program single-stepping. The debug facilities consist of a set of debug

control registers (DBCR0–DBCR3), a set of address compare registers (IAC1–IAC4, DAC1,

and DAC2), a configurable debug counter register (DBCNT), a debug status register

(DBSR) for enabling and recording various kinds of debug events, and a special debug

interrupt type built into the interrupt mechanism (see

Chapter 6.6.16: Debug interrupt

(IVOR15) on page 180,” for more information). The debug facilities also provide

mechanisms for software-controlled processor reset and for controlling the operation of the

timers in a debug environment.

Software debug facilities are enabled by setting the internal debug mode bit, DBCR0[IDM]. If

DBCR0[IDM] is set, debug events can occur and can be enabled to record exceptions in the

DBSR. If enabled by MSR[DE], these exceptions cause debug interrupts. If DBCR0[IDM]

and DBCR0[EDM] (EDM represents the external debug mode bit) are cleared, no debug

events occur and no status flags are set in DBSR unless already set. In addition, if

DBCR0[IDM] is cleared (or is overridden by DBCR0[EDM] being set), no debug interrupts

can occur, regardless of the contents of DBSR. A software debug interrupt handler can

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