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UM0434 Datasheet(PDF) 299 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 299 Page - STMicroelectronics |
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299 / 390 page  Debug support UM0434 300/391 The core defines the following debug events, which are described in Table 195: ● The debug counter debug events DCNT1 and DCNT2 ● The external debug events DEVT1 and DEVT2 ● The critical interrupt taken debug event (CIRPT) ● The critical return debug event (CRET) The core debug framework supports most of these event types. The following Book E– defined functionality is not supported: ● Instruction address compare and data address compare real address mode ● Data value compare mode A brief description of each of the debug event types is shown in Table 195. In these descriptions, DSRR0 and DSRR1 are used to store the address of the instruction following a load or store, assuming that the debug APU is enabled. If it is disabled, CSRR0 is used. |
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