UM0434 datasheet(287/390 Pages) STMICROELECTRONICS

287 / 390 page

External core complex interfaces

UM0434

288/391

Figure 57.

Read transfer with Wait-State, address retraction

Figure 58 shows functional timing for a burst read with wait-state transfer where the second

beat to addr x+8 is retracted and replaced with a new burst transfer.

Figure 58.

Burst read with Wait-State transfer, retraction

The first cycle of the burst incurs a single wait-state, and the burst is replaced by another

burst. Replacement by a single access is also possible.

nonseq

idle

addr x

addr y

addr w

single

data x

data z

data w

okay

Read with wait-state, address retraction

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

addr z

nonseq

seq

idle

addr x

addr y+8

addr y+16

incr

data x

data y

data y+8

data y+16

okay

Burst Read with wait-state

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

addr y

addr x+8

nonseq

UM0434 Datasheet(PDF) 287 Page - STMicroelectronics

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