UM0434 datasheet(283/390 Pages) STMICROELECTRONICS

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External core complex interfaces

UM0434

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Figure 53 shows an example of error termination.

Figure 53.

Read and write Transfers: instruction read with error,

data read, write, full pipelining

The first read request (addrx) is taken at the end of cycle C1 because the bus is idle. It is an

instruction prefetch.

The second read request (addry) is not taken at the end of C2 because the first access is

still outstanding (no

p_[d,i]_hready assertion). An error response is signaled by the

addressed slave for addrx by driving ERROR onto the p_[d,i]_hresp[2:0] inputs. This is the

first cycle of the two cycle error response protocol.

p_[d,i]_hready is asserted during C3 for the first read access (addr

x) while the ERROR

encoding remains driven on

p_[d,i]_hresp[2:0], terminating the access. The read data bus is

undefined.

In this example of error termination, the CPU continues to request an access to addry. It is

taken at the end of C3. During C4, read data is supplied for the addry read, and the access

is terminated normally during C4.

Also during C4, a request is generated for a write to addrz, which is taken at the end of C4

because the second access is terminating.

Data for the addrz write cycle is driven in C5, the cycle after the access is taken.

During C5, a ready/OKAY response is signaled to complete the write cycle to addrz.

In this example of error termination, a subsequent access remained requested. This does

not always occur when certain types of transfers are terminated with error. The following

figures outline cases where an error termination for a given cycle causes a pending request

to be aborted prior to initiation.

Figure 54 shows another example of error termination.

nonseq

idle

addr x

addr y

addr z

single

data x

data y

data z

okay

error

okay

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

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