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UM0434 Datasheet(PDF) 281 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 281 Page - STMicroelectronics |
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281 / 390 page ![]() External core complex interfaces UM0434 282/391 9.5.3 Address retraction Address retraction is the process of replacing a request with a new unrelated one. Although the AMBA AHB protocol requires an access request to remain driven unchanged once presented on the bus, higher system performance may be obtained if this aspect of the protocol is modified to allow an access request to be changed before being taken. Figure 57 shows an example of address retraction during wait state operation. Signal p_[d,i]_hready for the first request (addr x) is not asserted during C2, so a wait state is inserted during C3 until p_[d,i]_hready is recognized. Meanwhile, a subsequent request has been generated by the CPU for addry which is not taken in C2 since the previous transaction is still outstanding. The address and transfer attributes are retracted in cycle C3, and a new access request to addrz is requested and are taken at the end of C3 because the previous access is completing. Data for addrx and a ready/OKAY response is driven back by the slave device. In cycle C4, a request for addrw is made. The request for access to addrw is taken at the end of C4; during C5, the data and a ready/OKAY response is provided by the slave device. In cycle C5, no further accesses are requested. Figure 51. Read transfer with Wait-State, address retraction Figure 52 shows functional timing for a burst read with wait-state transfer where the second beat to addr x+8 is retracted and replaced with a new burst transfer. nonseq nonseq nonseq idle addr x addr y addr w single single single data x data z data w okay okay okay okay okay Read with wait-state, address retraction 12 34 5 6 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp addr z nonseq |
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