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UM0434 Datasheet(PDF) 277 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 277 Page - STMicroelectronics |
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277 / 390 page ![]() External core complex interfaces UM0434 278/391 The p_[d,i]_hburst signals indicate INCR for all burst transfers. The p_[d,i]_hunalign signal is negated. p_[d,i]_hsize indicates 64-bits, and all eight p_[d,i]_hbstrb signals are asserted. The burst address is aligned to a 64-bit boundary and increments by double words. Note that in this example four beats are shown, but in operation the burst may be of any length including only a single beat. Note: Bursts can be interrupted immediately at any time and can be followed by any type of cycle. No idle cycle is required. Figure 45 shows functional timing for a burst read with wait-state transfer. Figure 45. Burst read with Wait-state transfer The first cycle of the burst incurs a single wait-state. nonseq seq seq seq ... addr x addr x+8 addr x+16 addr x+24 incr data x data x+8 data x+16 data x+24 okay okay okay okay okay okay Burst Read with wait-state 1 23456 7 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp |
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