UM0434 datasheet(274/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

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Misaligned accesses

Figure 41 shows functional timing for a misaligned read transfer. The read to addr

x is

misaligned across a 64-bit boundary. Note that only half-word and word transfers may be

misaligned; double-word transfers are always aligned.

Figure 41.

Misaligned read, read, full pipelining

The first portion of the misaligned read transfer starts in C1. During C1, the core places valid

values on the address bus and transfer attributes.

The p_[d,i]_hwrite signal is driven low for

a read cycle. The transfer size attributes (

p_[d,i]_hsize) indicate the size of the transfer.

Even though the transfer is misaligned, the size value driven corresponds to the size of the

entire misaligned data item.

p_[d,i]_hunalign is driven high to indicate that the access is

misaligned. The

p_[d,i]_hbstrb outputs are asserted to indicate the active byte lanes for the

read, which may not correspond to size and low-order address outputs.

p_[d,i]_htrans is

driven to NONSEQ.

During C2, the addrx memory access takes place using the address and attribute values

which were driven during C1 to enable reading of one or more bytes of memory.

The second portion of the misaligned read transfer request is made during C2 to addrx+

(which is aligned to the next higher 64-bit boundary), and because the first portion of the

misaligned access is completing, it is

taken at the end of C2. The p_[d,i]_htrans signals

indicate NONSEQ. The size value driven is the size of the remaining bytes of data in the

misaligned read, rounded up (for the 3-byte case) to the next higher power of 2. The

p_[d,i]_hbstrb signals indicate the active byte lanes. For the second portion of a misaligned

transfer,

p_[d,i]_hunalign is driven high for the 3-byte case (low for all others). The next read

access is requested in C3 and

p_[d,i]_htrans indicates NONSEQ. p_[d,i]_hunalign is

negated, because this access is aligned.

nonseq

idle

addr x

addr x+

addr y

single

data x

data x+

data y

okay

123

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

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