UM0434 datasheet(272/390 Pages) STMICROELECTRONICS

272 / 390 page

UM0434

External core complex interfaces

273/391

Figure 39 shows another sequence of read and write cycles. In this example, reads incur a

single wait state.

Figure 39.

Multiple-Cycle reads with Wait-State, Single-Cycle writes, full pipelining

The first read request (addrx) is taken at the end of cycle C1 because the bus is idle. The

second read request (addry) is not taken at the end of cycle C2 because no ready response

is signaled and only one access can be outstanding (addrx). It is taken at the end of C3 once

the first read request has signaled a ready/OKAY response.

The first write request (addrz) is not taken during C4 because a ready response is not

asserted during C4 for the second read access (addry). During C5, the request for a write to

addrz is taken because the second access is terminating.

Data for the addrz write cycle is driven in C6, the cycle after the access is taken. During C6,

the addrz write access is terminated and the addrw write request is taken.

During C7, data for the addrw write access is driven, and a ready/OKAY response is

asserted to complete the write cycle to addrw.

nonseq

idle

addr x

addr y

addr z

addr w

single

data x

data y

data z

data w

okay

345

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

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