| Electronic Components Datasheet Search |
|
UM0434 Datasheet(PDF) 271 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
UM0434 Datasheet(HTML) 271 Page - STMicroelectronics |
|
271 / 390 page ![]() External core complex interfaces UM0434 272/391 Figure 38 shows another sequence of read and write cycles. This example shows an interleaved write access between two reads. Figure 38. Single-Cycle read, write, Read—Full pipelining The first read request (addrx) is taken at the end of cycle C1 because the bus is idle. The first write request (addry) is taken at the end of C2 because the first access is terminating (addrx). Data for the addry write cycle is driven in C3, the cycle after the access is taken. Also during C3, a request is generated for a read to addrz, which is taken at the end of C3 because the write access is terminating. During C4, the addry write access is terminated, and no further access is requested. nonseq nonseq nonseq idle addr x addr y addr z single single single data x data z data y okay okay okay okay 12 34 5 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |