UM0434 datasheet(267/390 Pages) STMICROELECTRONICS

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External core complex interfaces

UM0434

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of memory. Read data from the slave device for addrz is provided on the p_[d,i]_hrdata

inputs. The slave device responds by asserting

p_[d,i]_hready to indicate the cycle is

completing, and it drives an OKAY response.

Because the CPU has no additional outstanding requests,

p_[d,i]_htrans indicates

IDLE and the address and attribute signals are undefined.

Read transfer with wait state

Figure 34 shows an example of wait state operation. Because signal p_[d,i]_hready for the

first request (addrx) is not asserted during C2, a wait state is inserted until p_[d,i]_hready is

recognized (during C3).

Meanwhile, a subsequent request was generated by the CPU for addry which is not taken in

C2, because the previous transaction is still outstanding. The address and transfer attributes

remain driven in cycle C3 and are taken at the end of C3 because the previous access is

completing. Data for addrx and a ready/OKAY response are driven back by the slave device.

In cycle C4, a request for addrz is made. The request for access to addrz is taken at the end

of C4, and during C5, the slave device provides the data and a ready/OKAY response. In

cycle C5, no further accesses are requested.

Figure 34.

Read with Wait-State, Single-Cycle reads, full pipelining

Basic write transfer cycles

During a write transfer, the core provides write data to a memory or peripheral device.

Figure 35 shows functional timing for basic write transfers. Clock-by-clock descriptions of

activity in

Figure 35 follow.

nonseq

idle

addr x

addr y

addr z

single

data x

data y

data z

okay

1234

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

UM0434 Datasheet(PDF) 267 Page - STMicroelectronics

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