UM0434 datasheet(268/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

269/391

Figure 35.

Basic write Transfers—Single-Cycle writes, full pipelining

●

Clock 1 (C1)—The first write transfer starts in clock cycle 1. During C1, the core places

valid values on the address bus and transfer attributes. The burst type

(

p_[d,i]_hburst[2:0]), protection control (p_[d,i]_hprot[5:0]), and transfer type

(

p_[d,i]_htrans[1:0]) attributes identify the specific access type. The transfer size

attributes (

p_[d,i]_hsize[1:0]) indicate the size of the transfer. The byte strobes

(

p_[d,i]_hbstrb[7:0]) are driven to indicate active byte lanes. The write (p_[d,i]_hwrite)

signal is driven high for a write cycle. The core asserts transfer request (

p_[d,i]_htrans=

NONSEQ) during C1 to indicate that a transfer is being requested. Because the bus is

idle, (0 transfers outstanding), the first read request to addrx is considered taken at the

end of C1. The default slave drives a ready/OKAY response for the current idle cycle.

●

Clock 2 (C2)—During C2, the write data for the access is driven and the addrx memory

access occurs using the address and attribute values (driven during C1) to enable

writing of one or more bytes of memory. The slave device responds by asserting

p_[d,i]_hready to indicate the cycle is completing and drives an OKAY response.

Another write transfer request is made during C2 to addry (p_[d,i]_htrans = NONSEQ),

and because the access to addrx is completing, it is considered taken at the end of C2.

●

Clock 3 (C3)—During C3, write data for addry is driven, and the addry memory access

takes place using the address and attribute values (driven during C2) to enable writing

of one or more bytes of memory. The slave device responds by asserting

p_[d,i]_hready to indicate the cycle is completing and drives an OKAY response.

Another write transfer request is made during C3 to addrz (p_[d,i]_htrans = NONSEQ),

and because the access to addry is completing, it is considered taken at the end of C3.

●

Clock 4 (C4)—During C4, write data for addrz is driven, and the addrz memory access

takes place using the address and attribute values (driven during C3) to enable reading

of one or more bytes of memory. The slave device responds by asserting

p_[d,i]_hready to indicate the cycle is completing and drives an OKAY response.

Because the CPU has no more outstanding requests,

p_[d,i]_htrans indicates IDLE

and the address and attribute signals are undefined.

nonseq

idle

addr x

addr y

addr z

single

data x

data y

data z

okay

123

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

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